( 4 ) design and implement the alogrithm " delay balance in multiple level logic synthesis " ( 4 )设计并实现了“多级逻辑综合延迟均衡”算法。
2 . the logic synthesis process is studied in detail and the relative constraints are discussed 2 .详细研究了soc应用设计流程中的逻辑综合技术方法。
2002 , 149 : 119 - 128 . 9 sasao t . switching theory for logic synthesis . kluwer academic publishers , london , 1999 通过对给定的fprm真值矢量进行收缩,获得收缩后的真值矢量,然后把该矢量映射成逻辑表示式。
This dissertation detailedly investigate the symbolic logic and some typical techniques for low power fsm logic synthesis and optimization 论文详细讨论了低功耗有限状态机综合与优化中的符号逻辑和一些典型方法。
In electronics, logic synthesis is a process by which an abstract form of desired circuit behavior, typically register transfer level (RTL), is turned into a design implementation in terms of logic gates. Common examples of this process include synthesis of HDLs, including VHDL and Verilog.